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Weekly Lab Activities
There will be weekly
10
Lab Activities giving Digital Systems Design ability to students.
The EEE 251 laboratory work
will be performed using multiple platforms.
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The first platform will be
the breadboards: Students will physically build and test a number
of assignments in the laboratory using simple digital integrated
circuits. |
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The second platform will be
the simulation environments (in Xilinix ISE, like
ModelSim, NI Circuit Design Suit 11.0 – Multisim).
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The third platform will be a DIGILENT FPGA card (BASYS 2
or
SPARTAN 3E STARTER).
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In most labs, you will be using
at least 2 of these platforms In the second stage you are going to use the
Xilinx Design Environment for simulating and implementing more
complicated circuits in a Computer Aided Design (CAD) environment.
Lab Groups: Each student
should find a partner and form a 2-student team. The team will work
together in the lab. Students who have no lab partner will be assigned one
by TA.
The laboratory assignments will be implemented in the
laboratory of the Department of Electrical and Electronics Engineering. The
lab hour is 13:45-15:30 on Tuesday.
Lab Schedule
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W |
D |
Lab |
Lab
Experiments |
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4 |
18/10 |
Lab 1 |
Introduction to Laboratory
Equipment and Practice with Logic Gates: Introduction to
simple logic gates using breadboards and a simulation
environment. Practice with the ETS-7000 Digital-Analog
Training System and NI Multisim program. |
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5 |
25/10 |
Lab 2 |
Designing Combinational
Logic: 7 Segment LED Display: Building a logic circuit
to convert binary numbers into visible decimal numbers on a
7 segment display using your design and then a 7447 BCD
decoder chip. |
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6 |
1/11 |
Lab 3 |
Boolean Function
Minimization to SOP and POS: Simplifying a Boolean
function into the simplest SOP and POS forms using the K-Map
method, and implementing the simplified forms using first
AND, OR, and NOT gates, then NAND and NOR gates. |
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7 |
8/11 |
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No classes,
Kurban Bayram week |
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8 |
15/11 |
Lab |
Midterm Exam Week
Lab Tutorial: Introduction to Logic Design using
BASYS 2 FPGA boards and Verilog |
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9 |
22/11 |
Lab 4 |
Introduction to Logic Design
using an FPGA Board and Verilog: Designing combinational
logic that takes as input a 2-bit and 4-bit binary numbers
and generates control signals that will properly illuminate
a 7-segment display on the BASYS 2 FPGA board using Verilog.
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10 |
29/11 |
Lab |
Lab 4 continued |
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11 |
6/12 |
Lab |
Lab Tutorial: FSMs in
Verilog |
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12 |
13/12 |
Lab 5 |
Designing Counters on FPGA
Board Using FSM in Verilog: Design and implementation of
2 counters based on sequential logic using Finite State
Machine (FSM) in Verilog. The counters are controlled by a
START/STOP switch and a CLEAR button. The counters’ outputs
generate control signals that will illuminate a 7-segment
display on the BASYS 2 FPGA board. |
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13 |
20/12 |
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No Lab,
Midterm II |
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14 |
27/12 |
Lab 6 |
12-Button Keypad to
7-Segment Display: Simulating the 12-key keypad using
the 8 switches and 4 pushbuttons on the BASYS-2 board to act
as a key pad. |
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15 |
3/01 |
Lab 7 |
Automobile Above-Mirror
Display: FSM modeling of the 4-bit version of the
automobile above-mirror display which is described in the
Example 4.2 in the textbook (page 170). The Verilog and
BASYS-2 board will be used in the implementation. |
Lab Policies
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FPGA Board: Students will need to
purchase a
BASYS 2 FPGA board, made
by DILIGENT. Each lab partnership will need one. These boards will also
be used in other courses, COM 252 Computer Organization, COM 353
Microprocessors and COM 320 Embedded Systems. |
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Lab Partner:
Laboratory assignments will be carried out by teams of 2 students.
You must find a partner and register your team with the assistants at
the beginning of the first lab session. These teams will be valid for
all the lab assignments this semester. If you cannot find a partner, the
assistants will find one for you. |
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Attendance:
Attendance in the laboratory sessions is mandatory. For each lab that
you fail to attend without a valid excuse (such as a medical report),
you will receive the grade of 0. Missing more than 2 of the labs will
cause your overall grade for the lab to be FF. Leaving early or
coming late can be cause for giving the 0 grade, and is considered
missing that lab. Both partners in a lab group must stay until the lab
is completed and checked by the TA, or till the end of the lab time,
whichever comes first. |
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Preliminary Report:
Each group is required to prepare a preliminary report before coming to
the lab. The preliminary report should contain your circuit designs (or
simulation programs) together with any other information required in the
assignment. Therefore you should meet together with your lab partner
during the week or on the weekend before the lab, in order to solve the
given problem and decide on your logic circuit (or simulation programs).
You must submit your preliminary report to the lab assistant before
starting the laboratory work, at the start of the lab time. You
should therefore make a copy of it, to use during the lab session. On
the first page, you should write the names, ID numbers, and section
numbers of both members of the lab group, in the upper right corner. The
report should be stapled in the upper left corner if it is more than one
page, and not paper-clipped, pinned, or folded together. Turn in just
the report, without a folder or cover. |
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Lab Session: It is intended for
debugging, measurements and demonstration. Design and Wiring must be
done outside the lab before coming to the scheduled session. |
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Lab Demo: Using
the photocopy of the Preliminary Report, groups should implement their
design, test and debug it. Of course, it is possible that during the lab
session, you will find that your preliminary design was flawed and that
you need to make changes in order to get a correctly working circuit (or
simulation model). If errors are found in the demo, and if time allows,
the TA may give the group more time to fix the errors and a 'second
chance' to be graded. But in any case, all groups must demonstrate their
working (or partially working) circuits to the TA before the lab time
finishes, or else receive a grade of zero. |
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Grading: You will
be graded according to your preliminary report, your final
implementation of the lab (circuit or program) that you demonstrate,
your answers to any questions that are asked during or at the end of the
demo, and your participation in the lab. The percentages of these are
given on the Webpage posted in advance of each lab. |
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Makeup: Missing a
lab for an excused reason will allow you to make up that lab. Make-up
opportunities will be either in the same week (at another section's lab
time), or during a free week in the middle of the term, or at the end of
the semester. Students who miss lab must therefore contact us as soon as
possible with the reason for the absence, so that make up opportunities
can be arranged. |
Verilog Resources
Quick General Tutorials and
Information
In-Depth Tutorials and References
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Verilog Language Reference Manual copyright 1991 by OVI. 296 pages
of language definition and reference. Quite technical, a complete
reference, but superseded by the 1995 IEEE Verilog standard, 296 pages. |
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Verilog Tutorial In-depth tutorial by Deepak Kumar Tala,
238 pages. |
Structural and Behavioral Design
Verilog Examples
Computer Architecture using Verilog
General Links
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